The present invention relates to a technology of manufacturing a semiconductor device, and, for example, relates to the assembling of a semiconductor device including a wiring substrate on which a target mark is formed in the peripheral part thereof.
In Japanese Patent Laid-Open No. 2008-34681 (Patent Literature 1), there is described a technology that relates to a wiring substrate (multi-piece substrate) on which a target mark (target pattern) is formed on an extension line of each dicing region (scribing region, cutting region) in the peripheral part (part positioned around a plurality of device areas) thereof (for example, see FIGS. 16 and 18 of Patent Literature 1).